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dc.contributor.advisorHashemian, Rezaen_US
dc.contributor.authorChen, Cheng-Peien_US
dc.date.accessioned2016-02-12T17:00:47Z
dc.date.available2016-02-12T17:00:47Z
dc.date.issued1992
dc.identifier.urihttp://commons.lib.niu.edu/handle/10843/15398
dc.descriptionIncludes bibliographical references (pages [96]-97)en_US
dc.description.abstractThis thesis presents a method to use complementary metal-oxidesemiconductor (CMOS) technology to design and simulate a 32-bits high speed parallel adder, using CAD tools such as Mentor Graphics and CALMA (GDS II) systems. The method implemented to design this fast parallel adder is through the use of group increment. The design is carried out for a 32-bit fast parallel adder. The simulation results show an overall circuit delay about 16 ns using CMOS3 technology. This is much faster than carry look-ahead adder which is widely used as adder in a typical arithmetic logic unit (ALU).en_US
dc.format.extentix, 107 pagesen_US
dc.language.isoengen_US
dc.publisherNorthern Illinois Universityen_US
dc.rightsNIU theses are protected by copyright. They may be viewed from Huskie Commons for any purpose, but reproduction or distribution in any format is prohibited without the written permission of the authors.en_US
dc.subject.lcshMetal oxide semiconductors, Complementaryen_US
dc.subject.lcshParallel processing (Electronic computers)en_US
dc.titleA new algorithm and method for fast parallel adderen_US
dc.type.genreDissertation/Thesisen_US
dc.typeTexten_US
dc.contributor.departmentDepartment of Electrical Engineeringen_US
dc.description.degreeM.S. (Master of Science)en_US


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