A new algorithm and method for fast parallel adder
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This thesis presents a method to use complementary metal-oxidesemiconductor (CMOS) technology to design and simulate a 32-bits high speed parallel adder, using CAD tools such as Mentor Graphics and CALMA (GDS II) systems. The method implemented to design this fast parallel adder is through the use of group increment. The design is carried out for a 32-bit fast parallel adder. The simulation results show an overall circuit delay about 16 ns using CMOS3 technology. This is much faster than carry look-ahead adder which is widely used as adder in a typical arithmetic logic unit (ALU).